Parrallel Flash Loader

Hi Tricky,

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We are thinking about having the following setup in our new board (see attached image for architecture). We want to do this to give use access to the fast parrallel programming capability of the parrallel flash loader to get the Arria2 up in time to commicate on a PCIe link. We've had problems in the past with chips not coming up in time and then having the PCIe ignored, hence the fast parrallel programming.

The 2nd configuration interface comes from an ARM core that we have used to program other chips on other boards, but now we need it to program the flash rather than a chip. You cannot connect this to the PFL hence the custom IP needed (if we can make something that will fit!)

Another question is the format of the programming files. The Quartus programmer will only take pof, .jam and .jbc files, whereas the ARM core needs the data in .rbf format. Does this have any effect on the data in flash, or is that just because of the quartus programmer needing a file it can convert to JTAG? would the file in flash be the same at the end of the day, or is there some weird encoding I need to know about?

Any help on this greatly appreciated

Thanks :)

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I looked at the PFL and didn't like it. Instead I wrote my own:

http://www.ovro.caltech.edu/~dwh/carma_board/

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf

Its used twice on the board; once in a MAX II CPLD to configure the Stratix II system controller FPGA, and then again inside that system controller FPGA as the programmer for the four data processing FPGAs.

The MAX II version brings the Stratix II and PowerPC to life in time for the PowerPC PCI interface to be activated before the PCI bus has been enumerated.

Let me know if you would like the code for this controller. Its written in VHDL, and has testbenches.

Cheers,

Dave