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binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

P-tile Debug toolkit design changes

Hi there,

I am using Intel Agilex-F series development which uses P-tile. I am trying to enable P-tile Debug took kit on the Intel reference design. I am referring to Section 7.2 of P-tile Debug tool kit.

What I want to clarify is if I want o just view the P-tile status information and not configure anything to the registers, is it as simple as below steps:

1. Enable Debug Tool kit in Pcie IP configuration

2. Connect a clock to the xcvr_reconfig_clk port of the instantiation

3. Add a pin constraint to connect the xcvr_reconfig_clk to a 100 MHz clock source.

My question is do I need to drive any other signals on the xcvr_reconfig* interface to observe the DebugTool kit?

Thanks

Binu

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  • binupr's avatar
    binupr
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi Zying,

    Thank you for your reply.

    I am aware about the Section 7.2.1 and as mentioned in my original question connecting the clock source and pin assignment is clear to me. But what is unclear is if that is all is needed or do I need to drive any other signals on the xcvr_reconfig* interface to observe the DebugTool kit?

    Can you check with internal design team to clarify this? The document is inconclusive on this information.

    Thanks

    Binu

    • binupr's avatar
      binupr
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi Zying,

      Following up on the above question. Any update?

      I got the DebugTool kit with the above changes/as mentioned in P-tile Debug tool kit using Quartus 23.4. But I get some errors on the System Controller interface. Screenshot below for reference.

      Any input on this is much appreciated!

      Thanks

      Binu

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Binu,

    If the Debug Toolkit and the Hard IP Reconfiguration interface are enabled in the dynamically-generated design example, please check that the hip_reconfig_clk clock is connected to its respective clock source and the pin assignment is made properly.

    For further information, you may refer to link below, Section 7.2.1. Overview, https://www.intel.com/content/www/us/en/docs/programmable/683059/23-4-9-1-0/overview-85177.html

    Best regards,

    zying