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binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

P-tile Debug toolkit design changes

Hi there, I am using Intel Agilex-F series development which uses P-tile. I am trying to enable P-tile Debug took kit on the Intel reference design. I am referring to Section 7.2 of P-tile Debug too...
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ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi Binu,

If the Debug Toolkit and the Hard IP Reconfiguration interface are enabled in the dynamically-generated design example, please check that the hip_reconfig_clk clock is connected to its respective clock source and the pin assignment is made properly.

For further information, you may refer to link below, Section 7.2.1. Overview, https://www.intel.com/content/www/us/en/docs/programmable/683059/23-4-9-1-0/overview-85177.html

Best regards,

zying