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Altera_Forum's avatar
Altera_Forum
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14 years ago

Output Pin Driving Another Output Pin

Hello all,

I've run into an unusual problem. I'll start off by describing my goal: I'm designing a circuit that can test for short circuits and open circuits in a wiring harness. The wiring harness does not have a CAN bus or anything complicated like that - just simple wires.

Here's how it works

I have two CPLDs, one as a designated driving end (all pins are output) and another as an receiving end (all pins are input). The driving end CPLD is programmed to be a Serial In Parallel Out shift register and the receiving end is a Parallel In Serial Out shift register.

Let's assume all the wires in the harness are one-to-one i.e. no junctions. Let's also assume that there are only 8 wires. So, to test the first wire in the harness, the driving end register is loaded with 10000000. The receiving end also sees this and it all ends well. The driving end is then clocked and it reads 01000000. If the receiver also reads this, then that wire is OK.

But suppose there is a short circuit between wire 2 and 3. If that's the case, then the receiving end will read 01100000. This, too, is OK as we have detected the short and can take action.

But what happens at the driving end? The CPLD's pin 3 will be forcing 0V and pin 2 will be forcing 3.3V. The short circuit between pin 2 and 3 will result in two output pins connected together. I'm assume that a significant current will flow from pin 2 to pin 3 and damage could result.

Note that the shift registers/CPLDs are being driven by a microcontroller. Also note that the harness is usually quite large, around 200-300 wires. Some of which are one-to-many connections. This is why a CPLD was an attractive option as it allows me to program a large shift register and allows testing of a large harness with a relatively small circuit.

How can I handle such a problem?

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks, Cris.

    Here's what I came up with, as a whole. The MOSFET on the left hand side is for the transmitting end and the MOSFET on the right for receiving.

    The wire connecting the MOSFETs is our wiring thats to be tested and the output from the right MOSFET is connected to the CPLD - hence, its Drain is at 3.3V.

    http://i.imgur.com/PFuDZ.png

    My only issue is that I will end up with a lot of transistors on the board due to this. But if you feel this is the best solution, I'll go with it.

    But suppose I also want a reasonable current to flow through the harness, how would change this circuit? As it stands, the current will be very low because of the high input resistance of MOSFETs.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    But suppose I also want a reasonable current to flow through the harness, how would change this circuit? As it stands, the current will be very low because of the high input resistance of MOSFETs.

    --- Quote End ---

    Simply move to to the receiver end the resistor which pulls up to +12V.

    Leave on driver end only the MOSFET. Sorry I was not clear on this point.

    You are right: allowing current to flow through the harness is a good idea to make the system more immune to noise.

    I guess the switch in your schematic refers to the fpga output driven in open drain mode.

    This won't work correctly since gate capacitance would keep the active level indefinitely.

    In this configuration the fpga output must work in push-pull mode then a standard output, which drives both low and high level. But this would mean twice fpga pins because you need to route input signals elsewhere, and I think you can't afford it.

    If you want to use the original bidir i/o configuration I suggested, you must change the circuit in one of this ways:

    - use BJT instead of MOSFETS (the BJT base current will switch off the transistor)

    - place pull down resistors on MOSFET gates
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Simply move to to the receiver end the resistor which pulls up to +12V.

    Leave on driver end only the MOSFET. Sorry I was not clear on this point.

    --- Quote End ---

    Could you please elaborate on this bit? WHere should I move the resistor too on the receiving end?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I can't draw a schematic right now. I'll try to explain with words.

    Transistor gate/base near FPGA output.

    Then the harness wire connected to the drain/collector.

    The other side of the harness wire connects to:

    1- the 12V pull up resistor

    2- the gate/base of the receiving stage, near fpga input

    The pull up to 3.3V near fpga input.

    In other words, both resistors near to the receiver, while transistors are one per side.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    http://i.imgur.com/cwBb7.png

    How does this look? Is this what you suggested?

    One thing that bothers me is this: I will need the circuit to have 300 IO traces. If I put a transistor on each end and on each trace, I will need 600 transistors per board. Don't you think this is too excessive?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    How does this look? Is this what you suggested?

    --- Quote End ---

    No need for the 5k resistor connected to +12V on the left. The one on the right is enough.

    Another remark: why do you use an additional +5V supply on the right? Use 3.3V here too. If it's just a matter of MOSFET threshold, select a transistor with lower Vgs.

    --- Quote Start ---

    One thing that bothers me is this: I will need the circuit to have 300 IO traces. If I put a transistor on each end and on each trace, I will need 600 transistors per board. Don't you think this is too excessive?

    --- Quote End ---

    Those transistors and resistors don't make a great difference: those are small components.

    Remind you already have to place 300 traces and 300 connectors with wires, which make a more bulky (and costly) hardware.