Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Output file in Verilog

Hi there

I need your help!! I have to write test-bench results in an output file in verilog. I'm a beginner so I heve no idea how to do this.

thanks in advance

GP

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    yeah, I can search on internet too, but I need someone who explain me ( with some example) how to use correctly commands such as $fopen, $fwrite etc..

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Ok ....it goes like this....

    Syntax:

    $fopen("file_name","file_open_mode");

    different fopen modes

    "r" or "rb"

    Open for reading

    "w" or "wb"

    Truncate to zero length or create for writing

    "a" or "ab"

    Append (open for writing at end of file)

    "r+", "r+b", or "rb+"

    Open for update (reading and writing)

    "w+", "w+b", or "wb+"

    Truncate or create for update

    "a+", "a+b", or "ab+"

    Append; Open or create for update at end-of-file

    eg:

    integer op_file;

    op_file = $fopen("DATA_OUTPUT_FILE.txt","w");

    $fwrite(op_file,"%h\n",FILE_DATA); //FILE_DATA represents the DATA to be written into the file

    $fclose(op_file); //to release the memory allocated, If the opened files are not closed properly u may end up with wrong results. This shuld be done only after completely writing required data into the output file.

    Hope this helps u....feel free to contact

    Regards

    PKPM