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Altera_Forum's avatar
Altera_Forum
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16 years ago

Output file in Verilog

Hi there I need your help!! I have to write test-bench results in an output file in verilog. I'm a beginner so I heve no idea how to do this. thanks in advance GP
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thank you :)