Output enables on MAX7000s

In MAX7128S, output enable can be driven by dedicated nOE inputs or macro cells. Your code is supposes to work, if oe_n is defined accordingly. This can't be seen from your post.

Here' the rest of the module:

`timescale 1 ns/1 ps
module Custom_09xx
(
// Header for debugging on the FPGAArcade Custom Device
 PIN_1    ,
 PIN_2    ,
 PIN_3    ,
 PIN_4    ,
 PIN_5    ,
 PIN_6    ,
 PIN_7    ,
 PIN_8    ,
 PIN_9    ,
 PIN_10   ,
 PIN_11   ,
 PIN_12   ,
 PIN_13   ,
 PIN_15   ,
 PIN_16   ,
 PIN_17   ,
 PIN_18   ,
 PIN_19   ,
 PIN_20   ,
 PIN_21   ,
 PIN_22   ,
 PIN_23   ,
 PIN_24   ,
 PIN_25   ,
 PIN_26   ,
 PIN_27   
);
//=============================================================================
// I/O
//=============================================================================
input  PIN_1; // not connected
input  PIN_2; // not connected
input  PIN_3    ; // H2
input  PIN_4    ; // HSYNC
input  PIN_5    ; // HRESET
input  PIN_6    ; // VRESET
input  PIN_7    ; // VSH8
input  PIN_8    ; // VSH7
input  PIN_9    ; // VSH6
input  PIN_10   ; // VSH5
input  PIN_11   ; // VSH4
input  PIN_12   ; // VSH3
output PIN_13   ; // AB1
// input PIN_14; // GND
output PIN_15   ; // AB2
output PIN_16   ; // AB3
output PIN_17   ; // AB4
output PIN_18   ; // AB5
output PIN_19   ; // AB6
output PIN_20   ; // AB7
output PIN_21   ; // AB8
output PIN_22   ; // AB9
output PIN_23   ; // AB10
output PIN_24   ; // AB11
output PIN_25   ; // AB12
input  PIN_26   ; // VDD
output PIN_27   ; // not connected
// input  PIN_28; // not connected
//=============================================================================
// Parameters
//=============================================================================
parameter COUNT1 = 1'b0;
parameter COUNT2 = 1'b1;
//=============================================================================
// Internal wires/registers
//=============================================================================
wire       H2;
wire       hsync_n;
wire       hreset_n;
wire       vreset_n;
wire   vsh;
wire  ab;
wire  ab1;
wire  ab2;
reg   count1_4_0;
wire  count1_4_0_nxt;
wire  count1;
wire   count2_3_0;
wire  count2_11_4_nxt;
reg   count2_11_4;
wire  count2;
reg    loop_cnt;
reg    loop_cnt_nxt;
reg    hsync_count_7_0;
wire   hsync_count_7_0_nxt;
wire  hsync_count;
reg         count_sel;
wire        count_sel_nxt;
wire        oe_n;
reg         hreset_prev;
reg         vreset_sync;
reg         hreset_sync;
//=============================================================================
// Implementation
//=============================================================================
 // assign inputs
 assign H2 = PIN_3;
 assign hsync_n = PIN_4;
 assign hreset_n = PIN_5;
 assign vreset_n = PIN_6;
 assign vsh = {PIN_7,PIN_8,PIN_9,PIN_10,PIN_11,PIN_12};
 // synchronize reset signals
 always @(posedge H2 or negedge vreset_n) begin 
  if (!vreset_n)
   vreset_sync <= 1'b0;
 else 
   vreset_sync <= vreset_n;
 end
 
 always @(posedge H2 or negedge hreset_n) begin 
  if (!hreset_n)
   hreset_sync <= 1'b0;
 else 
   hreset_sync <= hreset_n;
 end
 
 always @(posedge H2 or negedge hreset_n) begin
  if (!hreset_n)
   hreset_prev <= 1'b0;
  else
   hreset_prev <= hreset_n;
 end
 // mux select to switch between count1 and count2 and control when they increment
 always @(posedge H2) begin
  if (!vreset_sync)
   count_sel <= COUNT2;
  else
   count_sel <= ~count_sel;
 end
 
 // count1 logic
 assign count1_4_0_nxt = (!hreset_sync) ? 5'd0 :
                         (!vreset_sync) ? 5'd6 : 
								 (count1_4_0 == 5'h1F) ? 5'd0 : count1_4_0 + 5'd1;
								 
 always @(posedge H2) begin
  if (count_sel == COUNT1)
   count1_4_0 <= count1_4_0_nxt; 
 end 
 
 assign count1 = {7'b0100000,count1_4_0};
 
 // count2 logic.
 // least significant nibble seems to track with hsync_count.
 assign count2_3_0 = hsync_count; 
   
 assign count2_11_4_nxt = (count_sel || !hreset_prev) ? count2_11_4 :
                                (ab2 === 8'hBF)       ? count2_11_4 - 8'h3F : count2_11_4 + 8'd1;
 always @(posedge H2 or negedge hreset_n) begin
  if (!hreset_n) begin
   count2_11_4 <= 8'h80;
  end else begin
   count2_11_4 <= count2_11_4_nxt;
  end
 end
 assign count2 = {count2_11_4,count2_3_0};
 
 // hsync count logic. Increments by 1 every hsync interval.
 assign hsync_count_7_0_nxt = hsync_count_7_0 + 8'd1;
 always @(negedge hsync_n or negedge vreset_n) begin
  if (!vreset_n) 
   hsync_count_7_0 <= 8'd0;
  else 
   hsync_count_7_0 <= hsync_count_7_0_nxt;	
 end
 
 assign hsync_count = {4'h3,hsync_count_7_0};
 assign ab2 = count2 + {2'b00,vsh,4'h0};         // vsh gets added to the middle nibble of count2 before it gets sent out
 assign ab1 = count1 + {4'h0,count2,5'h00}; // the last nibble of count gets added to the middle nibble of count1 before it gets sent out
 // mux to send out either of the 3 overall ab values
 assign ab = (~hsync_n)  ? hsync_count :
             (count_sel) ? ab2 : ab1;
				 
 // output enable				 
 assign oe_n = ~H2 | (~hsync_n & ~count_sel);
 // assign outputs
 assign PIN_27 = 1'bz;
 assign PIN_13 = (!oe_n) ? ab  : 1'bz;
 assign PIN_15 = (!oe_n) ? ab  : 1'bz;
 assign PIN_16 = (!oe_n) ? ab  : 1'bz;
 assign PIN_17 = (!oe_n) ? ab  : 1'bz;
 assign PIN_18 = (!oe_n) ? ab  : 1'bz;
 assign PIN_19 = (!oe_n) ? ab  : 1'bz;
 assign PIN_20 = (!oe_n) ? ab  : 1'bz;
 assign PIN_21 = (!oe_n) ? ab  : 1'bz;
 assign PIN_22 = (!oe_n) ? ab  : 1'bz;
 assign PIN_23 = (!oe_n) ? ab : 1'bz;
 assign PIN_24 = (!oe_n) ? ab : 1'bz;
 assign PIN_25 = (!oe_n) ? ab : 1'bz;
endmodule

No idea why OE function is not working. Did you check the drivers in simulation? The code synthesises without any serious warnings in Quartus.

Is there something I need to do in Quartus to tell the tool how I want to enable/disable the ouputs, or configure the global OE pins?

Hi, I had a similar issue a while back and this is the response I received from altera:

The OE function in the above code isn't related to global OE because it doesn't use an unconditional OE function for any output.