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SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
4 months ago

onnecting the F-Tile Reference and System PLL Clock IP out_coreclk_#i port to an IOPLL FPGA IP

Hello Intel forums, I'm trying to connect a out_coreclk from an F-tile Reference and System PLL Clock IP to an IOPLL. I understand that I cannot do this directly, so I'm following the workaround des...
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Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
3 months ago

Hi,

Could you verify if the port out_systempll_synthlock_i from F-tile system PLL IP gets asserted or not?

You could use this port ANDed with your system level reset to generate overall reset to the IOPLL.


Is the input clock to the system PLL always available and at the correct frequency?


I don't see any problem is generating a double frequency clock from the IOPLL.


Regards