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Honored Contributor
Honored Contributorone problem in simulate IP core.(SDRAM controller)
Hi,everybody. I creat a new project. And create a sdram controller with the plug-in manager. At last, the manager create a new subfolder named "testbench" . and there is a vhdl file(**_tb.vhd...
Altera_ForumHonored Contributor
Honored Contributoryou cannot use HDL test benches in Quartus II Simulator. you'll have to use ModelSim-Altera Starter Edition which is free to use an HDL test bench.
