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Altera_Forum's avatar
Altera_Forum
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14 years ago

onchip memory timing constraints

Hi guys!

I am capturing 1Mbit of 64 bit words at 100MHz with onchip memory on my DE2-115 board. All data is produced on the chip.

How do I need to add timing constraints? Do I need to set a constraint from the data and address registers to each Memory element? Is there a better way to introduce timing constraints? Everytime I introduce timing constraints I get critical warnings that timing constraints are not met ?? When I don't set constraints it seems to do okay.

How fast can I write to onchip memory and what is the maximum number of bits per word?

Thanks a lot! David

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    If your design is fully included in fpga (I mean if you only use onchip memory and no external ram or other i/o interfaces with timing requirements) then you only need a few timing constraints.

    Did you read the TimeQuest tutorial? You can also refer to the TQ guide by Rysc, which is very clear; you'll find it on the Wiki.

    The number of bits/word depends on your implementation. IIRC M9k blocks support up to 36bit width, but you can read more of them in parallel to emulate wider ports.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    On chip RAM is synchronous SRAM.

    You just need to constrain the clock; same as registers.

    If your constraints are not met , either

    a) they're wrong or b) Quartus can't produce a design that meets them.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks! I looked into these documents but need to read a lot more.

    Is it sufficient to

    - create_clock

    - derive_pll_clocks

    - derive_clock_uncertainty

    or do I also need to indicate the paths of the data to the onchip ram?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Yes, these are enough for basic timing analysis, if you don't have multicycles or false paths.

    Also enable timing driven synthesis in Quartus project settings.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks! It is working now, even with 128 bits per word. I want to achieve as many bits per word as possible. The Megafunction Wizard allows for 256 bits per word, but even with timing constraints for this word size, my data doesn't get saved properly.

    Do you know what the maximum of bits per word for the on-chip memory is?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Have you tried generating 128bpw memory blocks with the Wizard, then paralleling them to achieve a wider port?

    What do you mean with data "doesn't get saved properly": not saved at all? a few wrong bits? random saved data?

    You should also consider the problem can be due to the memory interface. Where does data come from? How do you perform writes? It could also be timing related, but I dare say a "functional" timing issue.