off chip ram issue.....

hi,

we created off-chip ram verilog code with avalon slave,but this off-chip ram is not visible for reset vector and exception vector of nios cpu and also this is not visible for data and programe memory in the nios IDE. so can you please provide a design example for above mentioned application

my contact is:

mobile1: 09866339896 (praveen)

mobile2: 09966360006 (thumma)