object assigned a value but never read - does this effect synthesis?

Hello,

I have the following small module which is intended to store the value 0xFF in a register when a button is pressed.

module connector_test(button, txd);
input button;
output reg txd;
reg  data;
always @(button) begin
    if(button==1'b0) begin
        txd <= 1'b0;
        data <= 8'hFF;
    end
    else begin
        txd <= 1'b1;
        data <= 8'b0;
    end
    
end
endmodule

I would expect the data register to be synthesized, but it seems to be completely disregarded and does not end up as part of the final circuit!

I get the following error during synthesis:

Warning (10036): Verilog HDL or VHDL warning at connector_test.v(5): object "data" assigned a value but never read

I'm not sure if the fact that the register is not read allows the synthesizer to assume that the logic is useless and automatically disregards it, or if something else is happening.

Any help in understanding this is appreciated!

-k