not compiling

The way round this error is to use either std_logic_arith package in all files, or the numeric_std package in all files. Mixing the two will give you the problems you are getting.

I highly recommened switching to the numeric_std package - it is a IEEE standard - std_logic_arith is NOT.

hi,

the divider compnenrt is working well, the thing is that i am tring to put it under another compnenet, the other componenet is using the arith.all library.

all the files go throgh complition, but as i am trying to run the testbench on modelsim i get an error saying that "# ** Failure: (vsim-3807) Types do not match between component and entity for port "a".

" for all compnenet ports, i have checked both the packege file and the enttity file' where types are defined and they are all set corectlly. do you know i get this error and how can i overcome it?

thanks

It is more than long enough... but if you really want to have twice the required amount of bits, I suppose a

div_res <= resize(a/b,2*N);

should do the trick.

thaks, its working

why cant i use 2N vector as the quantiet?it is long enough for the reult to fit in.

There are three issues involved with this short code snippet.

- a trivial one: the VHDL divide operator is slash '/' rather than backslash '\'

- an arithmetic one: the quotient must have the same length as a

- a VHDL library related one: std_logic_arith doesn't infer divider for signed type, you need to use numeric_std instead

P.S.: This code compiles correctly

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity div is 
generic (N : positive := 8 );
port ( a : in signed(N-1 downto 0);
b : in signed (N-1 downto 0);
div_res : out signed(N-1 downto 0)
);
end entity;
architecture behave_div of div is
begin 
div_res<=a / b;
end behave_div;