not compiling

There are three issues involved with this short code snippet.

- a trivial one: the VHDL divide operator is slash '/' rather than backslash '\'

- an arithmetic one: the quotient must have the same length as a

- a VHDL library related one: std_logic_arith doesn't infer divider for signed type, you need to use numeric_std instead

P.S.: This code compiles correctly

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity div is 
generic (N : positive := 8 );
port ( a : in signed(N-1 downto 0);
b : in signed (N-1 downto 0);
div_res : out signed(N-1 downto 0)
);
end entity;
architecture behave_div of div is
begin 
div_res<=a / b;
end behave_div;