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Honored Contributor
Honored Contributorno element generate when compiled
I compile a project everything is corrected but no element usage is generated , I have no idea at all , here attached my project file
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Altera_ForumLook at the warnings:
--- Quote Start --- Warning (10541): VHDL Signal Declaration warning at top.vhd(44): used implicit default value for signal "CLK_OUT_0" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. Warning (10541): VHDL Signal Declaration warning at top.vhd(45): used implicit default value for signal "reset_n" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. Warning (10541): VHDL Signal Declaration warning at top.vhd(51): used implicit default value for signal "wait_s" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. Warning (10492): VHDL Process Statement warning at top.vhd(152): signal "fifo_empty" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Warning (10492): VHDL Process Statement warning at top.vhd(195): signal "fifo_empty" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Warning (10873): Using initial value X (don't care) for net "slwr_d_n" at top.vhd(48) Warning (10873): Using initial value X (don't care) for net "done_d" at top.vhd(50) --- Quote End ---
