New ContributorNIOS II QSPI boot for Cyclone 10 GX
We are using the Cyclone 10CX220Y device with a Nios II CPU in our design, and want to boot it from QSPI (device MT25QU512).
So far, we are able to only start the .sof file from QSPI at power on, and not able to boot the Nios from QSPI.
We have followed chapter 5. Nios II Configuration and Booting Solutions from the Embedded Design Handbook (2018.11.12). Specifically, 5.2.4.3, QSPI boot using Boot Copier.
Our .sof file is ~9.2MB. We want to put the .sof file to offset 0x0, and the .hex file for the Nios to offset 0x00A0.0000 (10MB).
In our Quartus design (version 18.1) , we set the Nios Reset vector to 0x00A0.0000.
Reset vector memory is set to config_flash, our targeted QSPI device.
In the BSP editor, we uncheck all the Advanced.hal.linker boxes as the manual describes. Also, we set all linker sections to onchip_ram.
We then generate our BSP, and use the mem_init_generate make target to generate the .hex file.
Then we create a .jic file with the following content:
File/Data area Properties Start address
Flash Loader 10CX220Y
Boot info 0x00000000
SOF data Page_0 <auto>
Hex data absolute address 0x00A0.0000
Two differences we have here with the manual are:
- For us the ‘Boot info’ section shows up at offset 0x0, I do not see this in the manual
- Therefore, we are not able to select start address 0x0 for our SOF data, and instead select the <auto> option.
If we select 0x0 for SOF start address like the manual describes, we run into a Quartus error, saying this overlaps with the option bits from 0x0 to 0x1F.
Since the manual describes the QSPI boot only for MAX 10 devices, and refers to EPCQ programming for other devices, our own design flow differs from the screenshots.
After programming the generated .jic file to flash, after a power cycle we can see the .sof file has loaded and is running, but the Nios has not started.
Could you please comment on our procedure?
Could you advise what steps we should take to debug this problem?
