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Altera_Forum's avatar
Altera_Forum
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10 years ago

Nios II EPCS booting problem

Hi,

I am using DE0 nano and trying to boot Nios II from EPCS configuration device. I am following the procedure mentioned on this link (http://www.alterawiki.com/wiki/epcs_bootloaders).

The issue I am facing is that When I us Nios EDS to compile My small C test code and use that *.elf file the Nios II won't boot. However if I use Altera Monitor tool to compile the same code the Nios II boots perfectly.

The steps I am following are:

1- Add a separate on-chip memory of 1024 bytes (In addition to Main memory used by your application, either On-chip or SRRAM) in QSYS. Call it "boot_rom".

2- Set "Reset Vector" and "Exception Vector" offsets of Nios II to point at boot_rom.

3- Use "asm_bootloader" folder for boot loader code.

4- Edit "my_boot_loader_standalone.S" as follows:

a- Set Application code offset in EPCS memory --- ># define SOFTWARE_OFFSET 0x1c0000

b- Set EPCS Controller Base address defined in QSYS ----># define EPCS_FLASH_CONTROLLER_0_BASE 0x10800

5- Compile boot loader in Nios Command Shell by typing ----> make CODE_BASE=0x0

6- Copy "my_boot_loader_standalone.hex" to your project directory (Where *.qpf file exists)

7- Open QSYS and set the path for *.hex memory initialization file created earlier in boot_rom properties. Remove ".hex" from the file path and hit finish.

6- Generate QSYS and Compile the Quartus project to obtain *.sof file.

7- Obtain *.elf by compiling the application source code (Using Nios EDS / Command Shell / Altera Monitor Tool)

8- Edit "Boot_loader_script.s" as follows and copy it to the folder where *.elf file exists.

a-Assign "--change-addresses=" to the hex value of SOFTWARE_OFFSET in step-4.

b-Properly assign the correct *.elf file path

9- Run "Boot_loader_script.s" in Command Shell to obtain Intel-HEX version of the ELF file.

10- Now open "Convert Programming File" tool in Quartus II and generate *.jic file

a- Set the JIC file name

b- Select EPCS configuration device

c- Select Flash loader ---> Your FPGA part number

d- Add SOF file and Force the start address to 0x0

c- Add HEX file with Absolute addressing

11- open Quartus programmer and program the generated JIC file in your board. Power cycle

The screen shots of my Nios II BSP editor are attached. Can someone please let me know if I am missing anything ?

I have also noticed that the size of *.hex generated from EDS and Altera Monitor tool are very different, and EDS is generating a lot bigger file for the same C-code.

Thanks

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    SOLVED. For EPCS default bootloader you need to use mem_init and most importantly EPCS controller's clock input should be < 25Mhz.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    SOLVED. For EPCS default bootloader you need to use mem_init and most importantly EPCS controller's clock input should be < 25Mhz.

    --- Quote End ---

    I'm still having problems booting my Nios II from an EPCS16 device. I thought reducing the EPCS flash controller clock might fix it but no. I think the clock reduction is still needed so it has been reduced from 72MHz to 12MHz. The Nios II core still runs at 72MHz - could this be a problem?

    My system looks like this :-

    EPCS_flash_controller located at 0x00100000; Nios II reset vector set to 0x00100000. There is 64kB of on-chip memory starting at 0x01010000 and the Nios II exception vector is set to 0x01010020. The Nios II program runs correctly when using the debugger so the code's ok.

    I use these commands to generate the programming files

    sof2flash --epcs --input=C3D.sof --output=C3D.flash

    elf2flash --epcs --after=C3D.flash --input=C3D_comms.elf --output=C3D_comms.flash

    nios2-elf-objcopy –input-target srec –output-target ihex C3D_comms.flash C3D_comms.hex

    Next I use the Convert Programming File utility in Quartus II to combine the .sof and .hex into a .pof. The map file created looks ok with the .hex file starting from the next address after the end of the .sof. Looks like this

    BLOCK START ADDRESS END ADDRESS

    Page_0 0x00000000 0x00122F6B

    C3D_comms.hex 0x00122F6C 0x00126E8B

    Then I program the EPCS but when I try to run the program it fails.

    Any help much appreciated.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    I'm still having problems booting my Nios II from an EPCS16 device. I thought reducing the EPCS flash controller clock might fix it but no. I think the clock reduction is still needed so it has been reduced from 72MHz to 12MHz. The Nios II core still runs at 72MHz - could this be a problem?

    My system looks like this :-

    EPCS_flash_controller located at 0x00100000; Nios II reset vector set to 0x00100000. There is 64kB of on-chip memory starting at 0x01010000 and the Nios II exception vector is set to 0x01010020. The Nios II program runs correctly when using the debugger so the code's ok.

    I use these commands to generate the programming files

    sof2flash --epcs --input=C3D.sof --output=C3D.flash

    elf2flash --epcs --after=C3D.flash --input=C3D_comms.elf --output=C3D_comms.flash

    nios2-elf-objcopy –input-target srec –output-target ihex C3D_comms.flash C3D_comms.hex

    Next I use the Convert Programming File utility in Quartus II to combine the .sof and .hex into a .pof. The map file created looks ok with the .hex file starting from the next address after the end of the .sof. Looks like this

    BLOCK START ADDRESS END ADDRESS

    Page_0 0x00000000 0x00122F6B

    C3D_comms.hex 0x00122F6C 0x00126E8B

    Then I program the EPCS but when I try to run the program it fails.

    Any help much appreciated.

    --- Quote End ---

    Follow these steps:

    Nios II Booting using Default EPCS Bootloader:

    1- Add EPCS Flash Controller in Qsys

    2- Connect the Clk input of EPCS Flash Loader IP to a separate clock of < 25Mhz

    3- Set Reset Vector offset of NiosII to the Base Address of EPCS Flash Loader.

    4- Set Exception vector to any On Chip RAM

    5- Generate Qsys

    6- Open BSP Editor and set all linker regions to SDRAM / onchip memory

    7- Generate BSP and Build the BSP project

    8- Build Your C code and obtain *.elf

    9- Goto make targets->Build and run "mem_init_generate"

    10- From mem_init folder include *.qip file in your Quartus project and recompile to get *.SOF

    11- copy *.SOF and *.elf files in a separate folder i.e /output

    12- perform following in NiosII command Shell:

    1. Create a flash file for the hardware and software image

    sof2flash --input=<hwimage>.sof --output=hwimage.flash --epcs --verbose

    elf2flash --input=<elf file>.elf --output=swimage.flash --epcs --after=hwimage.flash --verbose

    2. Convert the flash images into Hex files

    nios2-elf-objcopy -I srec -O ihex hwimage.flash hwimage.hex

    nios2-elf-objcopy -I srec -O ihex swimage.flash swimage.hex

    3. Generate *.JIC file

    Create your jic file using Quartus® II Convert Programming File tool, add the Flash Loader and

    both hex files with absolute addressing option selected.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    Follow these steps:

    Nios II Booting using Default EPCS Bootloader:

    1- Add EPCS Flash Controller in Qsys

    2- Connect the Clk input of EPCS Flash Loader IP to a separate clock of < 25Mhz

    3- Set Reset Vector offset of NiosII to the Base Address of EPCS Flash Loader.

    4- Set Exception vector to any On Chip RAM

    5- Generate Qsys

    6- Open BSP Editor and set all linker regions to SDRAM / onchip memory

    7- Generate BSP and Build the BSP project

    8- Build Your C code and obtain *.elf

    9- Goto make targets->Build and run "mem_init_generate"

    10- From mem_init folder include *.qip file in your Quartus project and recompile to get *.SOF

    11- copy *.SOF and *.elf files in a separate folder i.e /output

    12- perform following in NiosII command Shell:

    1. Create a flash file for the hardware and software image

    sof2flash --input=<hwimage>.sof --output=hwimage.flash --epcs --verbose

    elf2flash --input=<elf file>.elf --output=swimage.flash --epcs --after=hwimage.flash --verbose

    2. Convert the flash images into Hex files

    nios2-elf-objcopy -I srec -O ihex hwimage.flash hwimage.hex

    nios2-elf-objcopy -I srec -O ihex swimage.flash swimage.hex

    3. Generate *.JIC file

    Create your jic file using Quartus® II Convert Programming File tool, add the Flash Loader and

    both hex files with absolute addressing option selected.

    --- Quote End ---

    Hi Danish, Thanks for the guidelines. I'm still struggling to get it to boot. I'm not sure how to implement step 10 of your guidelines. How do I 'include *.qip file' in my Quartus project? I'm using Quartus 12 sp2. There is no include option in Eclipse or Quartus. I finished up selecting Add/Remove Files in Project... in Quartus but you said 'From mem_init folder include *.qip file in your Quartus project'. Please advise?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    When you run "mem_init_generate" from eclipse, a folder named mem_init will be created under software/your_eclipse_project_name/. There you can fine *.qip file which you need to add in your Quartus project along with verilog/VHDL files.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi Danish.I meet the same problem.can you tell why should we do the step 9 and 10.thanks.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    Hi Danish.I meet the same problem.can you tell why should we do the step 9 and 10.thanks.

    --- Quote End ---

    These steps create a memory initialization file / boot loader to be used by EPCS controller during boot process.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    Hi Danish.I meet the same problem.can you tell why should we do the step 9 and 10.thanks.

    --- Quote End ---

    --- Quote Start ---

    These steps create a memory initialization file / boot loader to be used by EPCS controller during boot process.

    --- Quote End ---

    Thank you.I will have a try.

    http://www.alteraforum.com/forum/showthread.php?t=49409&highlight=mem_init_generate

    In the link. mellis mentiond " The FAE discovered that the NIOS II/e will not boot from the serial flash controller (Quartus 15.0) and the work-around is to use the NIOS II/f instead".

    Is that right?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Danish:

    I have a try,but it doesn't work.

    http://www.alteraforum.com/forum/showthread.php?t=49409&highlight=mem_init_generate

    In the link,Mellis mentioned "I opened an SR on this topic and got my local FAE from Arrow involved as well. The FAE discovered that the NIOS II/e will not boot from the serial flash controller (Quartus 15.0) and the work-around is to use the NIOS II/f instead. I posted this information to the SR and asked Altera to update the documentation to reflect this limitation, but I thought I would post the information here as well so that it shows up on Google searches.

    "

    Is that right?