Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Nios II CPU and Firmware access Problem

About the application: We have a multichannel application. Each channel design is based on a Altera Cyclone FPGA, which includes an internal NIOS II processor and an external program 32bit ASRAM (asy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

You are correct the Fast Output Register is the right way. But we already found out that the NIOS SOPC builder set those definitions on all ASRAM pins, so no additional delay can be spared inside the FPGA. The only solution we came up is degrading the Nios speed to 95MHz.

thanks and regards,

Menachem