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Altera_Forum
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7 years ago

NIOS II - Downloading ELF Process failed (Arria 10 FPGA Dev. Kit)

Hello, I’m trying to running ‘hello world’ project by making up basic Nios II system.

I encountered the error message : “Download ELF Process failed”.

- Target FPGA board : Arria 10 GX FPGA Development Kit

- Quartus ver. : Quartus Prime Standard 17.1.0

Let me show the detailed steps with figures. The figures are attached as a zip file.

Figure 1) I made a basic Nios II system using Nios II, JTAG UART, On-Chip Memory.

- Nios ver : Nios II/e

- On-chip mem size : 400000 bytes (Eclipsed showed that 32768 bytes does not sufficient)

Figure 2) I compiled them (generated verilog files from .qsys), got a .sof file and programmed the target FPGA using the .sof file.

Figure 3) I opened Eclipse and made the “Nios II Application and BSP from Template” using the .sopcinfo file

Figure 4, 5) Run configurations after building a hello world application.

Figure 6) During the run process, the Eclipse tried to connect target processor. However the console continuously showed that the target processor does not respond.

Figure 7) Finally Eclipse showed the error message : “Download ELF Process failed”

How can I solve this problem?

I would really appreciate it if you could give me any comment.

Thank you for reading :)

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    Hi,

    1. Check the reset pin/SW state, if we try to load/program elf into FPGA when reset is active(i.e Logic 0) we will face such issue.

    2. Create a new eclipse project and check.

    Also, Check the old threads

    https://alteraforum.com/forum/showthread.php?t=34954

    https://alteraforum.com/forum/showthread.php?t=41189

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)
  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    @ OP

    This usually happens when you uncheck active low reset check box in the clock source component. And make sure you have given the pins constraints like BH33 (stratix 10) and reset pin to A19. This tools wont alert you while configuring. But throws the error message after consuming a precious time. so careful.
  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    to Anand Raj Shankar, anilinaltera

    Thank you for your reply. I just solved my problem from your comments.

    The main cause was that I didn't assign 'clock' and 'resetn' signal to the appropriate pins of Arria10 FPGA.

    I assigned 'clock' signal to PIN_AU33 (1.8V 50MHz reference clock) and 'resetn' signal to PIN_U11 (User Defined Push Button).

    Then Nios gave me perfect response.

    kiyeop