Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Nios Boot up from EPCS

I am having trouble booting up my Nios C code from EPCS. I am building my own FPGA board, not using a demo board. Here are the steps I am following: 1) In Qsys define nios ii reset vector to ep...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

OK. Here is my solution.

Instead of generating a pof file I generated a jic file in Convert Programming Files. Here you can select you target FPGA device and target flash/epcs device. The main point is to NOT compress the SOF file. However, when you do this, the sw.hex relative address is no longer 0x1. To find this value I first tried to generate with the improper offset. This produces an error that tells the address space of the sof file. Then you can adjust the sw.hex file address to be 1 byte after the uncompressed sof file.

The JIC file is programmed in JTAG mode instead of the sof file. (I have yet to try this same uncompressed trick with a pof file).

Now the FPGA will be configured from the EPCS flash on power up of the board.

Why this complete method of configuring the EPCS device and the FPGA is so convoluted, is a mystery to me. It seems like such a crucial process should be well streamlined....

So in summary if you follow all the steps EXCEPT for step 6e --> do not compress the sof, and if you manually set up the address space for the hex file properly, then the configuration process and nios boot up will work properly.