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Altera_Forum
Honored Contributor
Honored ContributorNewbie can't load data into fifo
I am new to FPGAs. I'm unable to clock data into the mega function FIFOs (both lpm_fifo_dc and dcfifo) in the simulator. I assume I'm doing something wrong, so I've retraced my steps for creating a...
Altera_ForumHonored Contributor
Honored ContributorSorry, I should have been more specific. You need an active clock on rdclk.
Jake
