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Altera_Forum's avatar
Altera_Forum
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17 years ago

newbie asks about "LATCH primitive ... is permanently disabled"

Folks, I have a DE1 (CycloneII starter board) to learn VHDL and Quartus. I developed and successfully tested my bit-shifting FIFO UART on the DE1. With this design functional, I'd like to move it ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

FvM,

Thanks for the reply, I understand your point. However, using the same source code, I get the warnings compiling for MAX3000 part and don't get warnings for a Cyclone II. I don't fully understand the underlying family differences, i've only been working with VHDL for 3 days. I figured that if my design wasn't synthesizable, I'd get an error.

So I'm still confused. Anyone have other pointer for me?

Thanks,

Craig

--

Dr. Craig Hollabaugh, [email protected], 970 240 0509

Author of Embedded Linux: Hardware, Software and Interfacing

www.embeddedlinuxinterfacing.com (http://www.embeddedlinuxinterfacing.com)