New Verilog/Quartus user

Once you get through that book I also recommend reading this:

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

This will give you an idea of how to structure your HDL to best map into an FPGA.

Another thing I recommend you pay special attention to are the differences between synthesizable and simulation code. What you write in say a simulation testbench may not necessary work in real hardware. So if you learn the difference early on you won't get into the pitfalls that others seem to find themselves in.

Quartus also has a templates menu option under the 'edit' menu that you can take a look at too for small examples of things like coding RAMs/ROMs, flip flops, math operators, statemachines, etc...