New to VHDL: Understanding timer.vhd implementation

I doubt it. Im guessing it was either intended to be upgraded to a real clock enable, or it was once a clock enable and found it easier to force it to one rather than removing the code the process.

I have a question for you - where are there unnessasary std_logic qualifications all over the code?

clk_en <= '1'; is perfectly acceptable. You only need std_logic'() when you need to qualify something is a std_logic rather than a bit or a character. When a signal is already defined as a std_logic, there is no need to qualify its assignment. std_logic'(signal) is even more unnessasary - the signal is already a std_logic.