Honored Contributorgood evening! im new in verilog and im interested in verilog programming. they said that some industries preferred verilog instead of vhdl? is is true? as a starter, what software will i use to compile and execute my verilog file? is it graphical or text-based?
thank you and looking forward for your answers.
Honored Contributormost of the CAD tools support both verilog and VHDL.
the syntax of verilog is like C language but vhdl is like pascal, I think. you can use Modelsim to compile and simulate your HDL codes.it has a graphical user interface too.there are student version and altera web edition version if you don't want to pay for it now.Honored Contributorsame here Duryan
Honored ContributorVHDL is not like pascal. It's like ADA.
VHDL is strong typed language and Verilog is weak typed language. Read some tutorials before deciding which one to use. I personaly think that VHDL is better.Honored ContributorI'm not going to say which language is better..... for the record I started with VHDL but like verilog more now :)
Anyway my recommendation would be to create a new verilog and VHDL file in Quartus II, then select "Edit" --> "Insert Template" and compare the templates between the two languages. In general verilog is typically more compact but like others have said it's not as strong typed so if you code something incorrectly you may not find out right away like you do with VHDL. If you have developed software before in C I think you'll have an easier time starting with verilog since the syntax is very similar (in fact when I'm jumping back and forth between hardware and software I often code in the wrong language forgetting what I'm doing :))Honored ContributorAgree with most of the folks here.
Verilog is more C like, thus for a beginer with some C programming knowledge and Digital electronics background it would be easier with verilog. However VHDL and Verilog compared and contrasted, have their own merits and its more to do with companies using there legacy stuff. e.g. Military and Aero industries prefer VHDL where as most other folks use Verilog and even system verilog and other newer languages(system C,specman e, vera etc). You may just search over the web for "verilog tutorials" and you would get plethora of information.
