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Altera_Forum
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7 years ago

need set_max_delay understanding

Hi all, Can please some one explain that what is set_max_delay and what will happen it if is used on two clocks to meet setup slack inside FPGA? Kind regards Mohsin
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Altera_Forum
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7 years ago

Hi sstrell,

Thank you.

1- The input devices are FPGA boards and clocking out the data at 40MHz. There is a customized serial interface between input FPGAs and main FPGA without any clock reference. The design is already working without any constraints and we want to constraint it to increase the processing speed of algorithm in the main FPGA.

2- Yes, it is truly asynchronous, I will false path it but still I have to write the constraints with reference to a clock.

kind regards

Mohsin