need set_max_delay understanding

1) Remember that the virtual clock is the clock that drives the upstream (input) device. It defines the launch edge while your 160 MHz clock is the latch edge. What clock speed is driving that device?

2) If it's truly asynchronous, just false path it. If it's not meant to be truly asynchronous, synchronize it with a register chain (at least two registers) and false path the input from the device port.