need set_max_delay understanding

Hi sstrell,

Thank you for your reply.

Can you please help me with following queries.

1- Clock input to FPGA is 16MHz and is going to a PLL, which generates the 160 MHz clock, now this PLL clock is used as reference clock for input signals to FPGA. The question is that how will I write the constraint for input signals i.e. w.r.t 16 MHz or 160MHz? I have tried to do it like this, created a virtual clock of 160MHz and set_input_delay w.r.t to virtual clock but it gives timing failure with reference to PLL generated clock

2- One of the input signals is an I/O signal and also asynchronous (coming from a micro-controller) how I can write the I/O constraints for this?

Kind regards

Mohsin