Need Opinion: Timing Closure with Incremental Compilation and Design Space Explore

For item 1), that should work. Synthesis is actually supposed to find PLLs in empty partitions and bring them out(assuming the connections are direct, which they should be). I've seen this work on other designs. That being said, setting the top-level to Empty isn't known very well and therefore doesn't get used a lot.

For 2), I wonder if it was counting open areas in the LABs of the post-fit logic. Were you using 12.1? The Logic Resource counting is different(although the Logic Utilization should essentially be the same, just the way it's shown and built up is different). I wonder if you could look at utilization in the hierarchy browser and Fit report and see what went up? (I'm guessing either the utilization for that partition went up, or the Estimated Recoverable ALMs dropped). If a block of logic is set to post-fit, I do believe you're not going to get a lot of logic put in that region, even if you can see a lot of holes, because that's a significantly more difficult fitting problem.

If possible, filing SRs would help Altera debug.

Thanks for the info.