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Altera_Forum
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13 years ago

Need Opinion: Timing Closure with Incremental Compilation and Design Space Explore

I was given a design with a long pipeline of logic path running at 300 Mhz, and DDR3 memory controller at 166 Mhz in Arria V GX with Quartus II 12.1 SJ Version. There were initially 8000+ timing e...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I'm guessing you've got a lot of paths that are close to meeting timing, but the fitter can't get them all to converge. With higher clock rates like 300MHz, there aren't any paths that have too much slack, making the problem more difficult.

- Try to determine which paths show up the most often.

- See if they can be modified in anyway to improve timing. Pipelining of course, but register duplication, etc. may be helpful. I find when I'm really close, some straightforward duplication is often enough to get a little bit more and hopefully get that last bit out. The following might be helpful:

http://www.alterawiki.com/wiki/register_duplication_for_timing_closure

I'd also be curious of any anecdotes of what worked or didn't work out of the Tips for Incremental Compilation and LogicLock. Good luck.