Honored ContributorI failed to send values between 2 modules. Please help me fix it:
// top.v
module top;
src s(
.value (value)
);
wire value;
des d(
.value (value)
);
endmodule
// src.v
module src(value);
output value;
assign value = "Hello";
endmodule
// des.v
module des(value);
input value;
$display("%s", value); // Display nothing
endmodule
Honored ContributorJust a guess, but move your wire statement to the top, before it is used, i.e.,
module top;
wire value;
src s(
.value (value)
);
des d(
.value (value)
);
endmodule
That didn't work. :p
Honored ContributorHonored ContributorErm, looking back at your original code, you are trying to transmit a string via a single wire. I don't think you can do that in Verilog. You need to look for a Verilog example of how to use strings, I think you need a multibit wire ... but I don't code much in Verilog.
Cheers, DaveHonored ContributorThanks for the tip. That was a multibit issue, and I just worked that out. :)
