Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorNeed help with Verilog sending values
I failed to send values between 2 modules. Please help me fix it:
// top.v
module top;
src s(
.value (value)
);
wire value;
des d(
.value (value)
);
endmodule
// src.v
module src(value);
out...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- That didn't work. :p --- Quote End --- Why don't you post your code and the code for your testbench. If you don't have a testbench, then its time to write one :) Test the testbench using Modelsim, and then synthesize your design using Quartus. Cheers, Dave
