Need help with 3 bit parity generator!

The question:

To design a 3-bit parity generator/checker that has three data inputs (A to C) and two odd/even parity outputs (odd_out and even_out). When the number of high level input is odd, odd_out is kept HIGH and even_out output LOW. Likewise, if the number of high level input is even, even_out is kept HIGH and odd_out LOW. The design of this generator is to be written in VHDL. Produce the truth table for this generator and treat C as the MSB.

Expected simulation results is at the attached file.

True parity generator would be:

process (a, b, c)

odd_out <= ((a xor b) xor c);

even_out <= (not odd_out);

end process;

If you actually want both outputs low when inputs are all low, then

process (a, b, c)

if (a or b or c) then

odd_out <= ((a xor b) xor c);

even_out <= (not odd_out);

else

odd_out <= '0';

even_out <= '0';

end if;

end process;

--- Quote Start ---

True parity generator would be:

process (a, b, c)

odd_out <= ((a xor b) xor c);

even_out <= (not odd_out);

end process;

If you actually want both outputs low when inputs are all low, then

process (a, b, c)

if (a or b or c) then

odd_out <= ((a xor b) xor c);

even_out <= (not odd_out);

else

odd_out <= '0';

even_out <= '0';

end if;

end process;

--- Quote End ---

When i tried your code, it gives 4 errors when i tried to compile.

Error: tyoe of identifier "a" does not agree with its usage as boolean type

Error: tyoe of identifier "b" does not agree with its usage as boolean type

Error: tyoe of identifier "c" does not agree with its usage as boolean type :(

This will work:

library ieee;
use ieee.std_logic_1164.all;
entity paritygen is
port (a, b, c : in std_logic;
odd_out, even_out : out std_logic);
end paritygen;
architecture work of paritygen is
 
begin
  process (a, b, c)
    begin
 
    if (a = '1') or (b='1') or (c='1') then 
      odd_out <= ((a xor b) xor c);
      even_out <= not ((a xor b) xor c);
    else 
      odd_out <= '0'; 
      even_out <= '0';
    end if;
 
   end process;
   
end;