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Altera_Forum's avatar
Altera_Forum
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15 years ago

Need help with 3 bit parity generator!

Hello, I'm tasked to design a 3 bit parity generator by using VHDL code but i can't seem to get it right. Can anyone help me with this? Thanks in advance! This is what i have done: lib...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

True parity generator would be:

process (a, b, c)

odd_out <= ((a xor b) xor c);

even_out <= (not odd_out);

end process;

If you actually want both outputs low when inputs are all low, then

process (a, b, c)

if (a or b or c) then

odd_out <= ((a xor b) xor c);

even_out <= (not odd_out);

else

odd_out <= '0';

even_out <= '0';

end if;

end process;