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Altera_Forum's avatar
Altera_Forum
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15 years ago

Need help with 3 bit parity generator!

Hello, I'm tasked to design a 3 bit parity generator by using VHDL code but i can't seem to get it right. Can anyone help me with this? Thanks in advance! This is what i have done: lib...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

This will work: 

library ieee;
use ieee.std_logic_1164.all;
entity paritygen is
port (a, b, c : in std_logic;
odd_out, even_out : out std_logic);
end paritygen;
architecture work of paritygen is
 
begin
  process (a, b, c)
    begin
 
    if (a = '1') or (b='1') or (c='1') then 
      odd_out <= ((a xor b) xor c);
      even_out <= not ((a xor b) xor c);
    else 
      odd_out <= '0'; 
      even_out <= '0';
    end if;
 
   end process;
   
end;