Need help with 3 bit parity generator!

This will work:

library ieee;
use ieee.std_logic_1164.all;
entity paritygen is
port (a, b, c : in std_logic;
odd_out, even_out : out std_logic);
end paritygen;
architecture work of paritygen is
 
begin
  process (a, b, c)
    begin
 
    if (a = '1') or (b='1') or (c='1') then 
      odd_out <= ((a xor b) xor c);
      even_out <= not ((a xor b) xor c);
    else 
      odd_out <= '0'; 
      even_out <= '0';
    end if;
 
   end process;
   
end;