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Altera_Forum's avatar
Altera_Forum
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15 years ago

Need help with 3 bit parity generator!

Hello, I'm tasked to design a 3 bit parity generator by using VHDL code but i can't seem to get it right. Can anyone help me with this? Thanks in advance! This is what i have done: lib...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The question:

To design a 3-bit parity generator/checker that has three data inputs (A to C) and two odd/even parity outputs (odd_out and even_out). When the number of high level input is odd, odd_out is kept HIGH and even_out output LOW. Likewise, if the number of high level input is even, even_out is kept HIGH and odd_out LOW. The design of this generator is to be written in VHDL. Produce the truth table for this generator and treat C as the MSB.

Expected simulation results is at the attached file.