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Please notice, that only the obvious syntax errors are corrected.
I should add a comment on the recursion problem. When executing a sequential computer program, the number of recursions is determined at run time, depending on the actual data. In hardware design, the maximum number of recursions must be known at compile time to generate the logic for it.
I added a constant parameter to the function to clarify the maximum number of recursions. hermitePolynomial_3.vhd is the respective text. Then Quartus doesn't run immediately into a stack error. But Quartus may be still unable to compile the design because the involved parallel logic is too complex. With d_max = 7, about 15k LEs are consumed, I didn't want to try for larger numbers.
Besides huge logic cell consumption, the problem of missing pipeline registers can't be solved by the recurcsive description, I fear. With d_max = 7, a delay of about 70 ns with Cyclone III is calculated by the timing analyzer.
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FvM,
Thanks a lot for your attention to my question and for your explanation + code. I'll refer it and try to modify my work.
Honored Contributor
