Need help for VHDL recursive function

heres a quick example: f = (a * b) + (c * d). It has a latency of 2 clock cycles (ie. result F appears 2 clocks after A,B,C and D inputs. You can put in 1 input every clock cycle, and result is produced every clock cycle)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity func is
  port (
    clk        : in  std_logic;
    
    a,b,c,d    : in  unsigned(7 downto 0);
    
    f          : out unsigned(16 downto 0)
  );
  
end entity func;
  
architecture rtl of func is 
  signal AxB, CxD : unsigned(15 downto 0);       
begin
  
  process(clk)
  begin
    if rising_edge(clk) then
      
      AxB  <= a*b;
      CxD  <= c*d;
      
      f    <= ('0' & AxB) + ('0' & CxD);      
    end if;
  end process;
  
  
end architecture rtl;