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Altera_Forum
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10 years ago

Need help for LVDS deserializer

Hello, I need to interface an ADC from Maxim (MAX1437) which have LVDS output (clock, frame, an 12 bits data wide) with a MAX10 FPGA. The goal is to deserialize data's. I develop from Quartus...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hello,

I developed an intermediate project that consist to deserialize data only on even bit. This one is correct when I simulate it in functional mode. But the datas on outputs device are not valid that is confirmed by Signal Tap software. I would like run gate-level simulation to understand where is the problem but no sdf file are generated during compilation. So, is there any restriction to do this under Quartus II 15.0 with MAX10 devices ?

Thanks,

Stéphane