Need help for LVDS deserializer

Hello,

I did exactly what you advised me. I configured Altera Soft LVDS with SERDES factor of 6 and with internal PLL first to begin. Because I'm using Altera MAX10 Evaluation kit, I planned to choose pins 52 and 50 (differential pair LVDS) for "input frame" (that is PLL input signal).

But, after compilation, I has error message like that :"Error (176554): Can't place PLL -- I/O "input frame" pin I (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device".

So, I did another compilation without assignment pin directive for this signal, and Quartus fitter allocated input signal on pins 28 and 27.

I've not tested it yet, but, do you know if PLL input signal will not be able allocate any I/O LVDS pin ?

Best regards,