Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Need help for LVDS deserializer

Hello, I need to interface an ADC from Maxim (MAX1437) which have LVDS output (clock, frame, an 12 bits data wide) with a MAX10 FPGA. The goal is to deserialize data's. I develop from Quartus...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

You need to use the 'Altera Soft LVDS' IP. Refer to the 'soft deserializer' section, in the 'max 10 lvds receiver design' chapter, of the "max 10 high-speed lvds i/o user guide (https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0cb8qfjaaahukewjdqy69spfjahucqxokhs1ucea&url=https%3a%2f%2fwww.altera.com%2fliterature%2fhb%2fmax-10%2fug_m10_lvds.pdf&usg=afqjcnedbunwv-hclbcgzblt7-uhz7h8yg&bvm=bv.107467506,d.d24)".

Search for 'LVDS' in the IP catalog search in Quartus to start configuring the IP. Set it up for 'RX' only, set your data and clock rates. I suggest you use a 'SERDES factor' of 6 (as 12 isn't available). This will give you half of the result every 6 'VCLKOUT' cycles.

Ensure the VCLKOUTP/N signals connect to dedicated clock pins on the FPGA. Connect VOUTP/N to a suitable P/N pin pair. Configure your FPGA pin assignments for LVDS.

Cheers,

Alex