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Altera_Forum's avatar
Altera_Forum
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16 years ago

Need help : implement Gigabit Ethernet

Hello, I'm new on this forum, so I hope that I'll be clear with my question. I'm currently working on Cyclone III FPGA Development Kit with the EP3C120F780C7N. For my project I have to etabli...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

When you configure a FPGA with a time limited sof file, you'll have an alert box telling you that you are in Opencore evaluation mode. It is very important not to close that window! If you do the CPU will stop working. That's why I suggested to launch the Quartus programmer as a separate application, so that you can use SignalTap even if you have a time limited sof file.