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Altera_Forum's avatar
Altera_Forum
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14 years ago

NCO phase drift

Hello,

I have an NCO generating a 60 Hz sine output.

input clk = 10 khz

phase accumulator precision = 32 bits

angular resolution = 32 bits

magnitude precision = 10 bits

phase increment value = fixed at 25769804

It is a parallel cordic implementation.

My problem is I get a phase drift over time.

I am a new user and would like to understand this better. Any insight would be appreciated.

Thanks

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    To allow PLL locking in "finite" time, you should allow at least 0.5 or 1 Hz frequency adjustment, I think. The PLL filter has to be designed for a respective lock range in case of an XOR or similar phase detector without frequency comparison

    I'm using mains frequency PLLs mostly with "hybrid" (ADC based) analog phase detectors, because typical power electronic related designs involve mains voltage measurement channels anyway.