Honored ContributorHello,
I have an NCO generating a 60 Hz sine output. input clk = 10 khz phase accumulator precision = 32 bits angular resolution = 32 bits magnitude precision = 10 bits phase increment value = fixed at 25769804 It is a parallel cordic implementation. My problem is I get a phase drift over time. I am a new user and would like to understand this better. Any insight would be appreciated. Thanks
Honored ContributorHonored ContributorHonored ContributorThank you for your quick response and information, it is a very good reference.
Honored ContributorHonored ContributorIt is true that if your tuning word is rounded(in any way) it means phase drift will occur no matter what resolution you use. see my matlab model here:
http://www.dsprelated.com/showcode/240.php For 60Hz you will need your clock to be integer multiple of 60 e.g. 60KHz and then your modulo can not be power of 2.Honored ContributorYou don't need matlab to see, that accumulating the said tuning word of 25769804 with an input frequency of 10e3 results in an exact output frequency of 60. No "rounding" is involved.
10000*25769804 = 60*2**32 The reported problem is apparently related to a frequency deviation of the crystal respectively mains frequency fluctuations. F.Y.I.: http://en.wikipedia.org/wiki/mains_frequency#long-term_stability_and_clock_synchronization P.S.: kaz is right about a small rounding. I have been fooled by my pocket calculator. In fact the tuning word is high by about 10 ppb. At least 3 orders of magnitude below expectable crystal accuracy. The exact tuning word would be 25769803.78Honored ContributorYes you will get 60Hz "exactly". the issue isn't about frequency but its phase (without affecting frequency due to very slow buildup of fractional error).
the value 25769804 has been rounded and its fraction discarded. But I suspect in this post the problem is due to clock drift itself rather than NCO drift, however the post has presented itself as NCO problem.Honored ContributorIn addition, if the problem is somehow about mains frequency synchronization, an all digital PLL should be considered.
Honored ContributorThank you all for your help...yes the problem is about main frequency synchronization. I have an xor phase detection circuit setup and can implement an all digital PLL which is where this all was going but my concern was if there is a constant phase "drift" the loop would saturate and not be able to control the phase.
Honored ContributorIf I understood you are trying to lock to the mains 60Hz using NCO.
In this case I assume you will be doing that by changing NCO tuning word up and down from an initial value such that it keeps tracking the mains. In this case the drift I was referring to does not really apply and the loop should be able to lock provided your ref clock is good enough.
