Hi i'm trying to test a fixed point filter on a FPGA board, my filter has an input of 16 bit, but the maximum value it can take without saturation is 1023 which is 11 bits. so far the only signal i've been using to is the NCO megafunction. when i set the NCO to have a magnitude of 16 bits i get severe distortion and loss of precision, i cant change the NCO to have a smaller number of bits or i get a bit mismatch, and i cant reduce the number of bits of the filter because i get distortion and loss of precision again. i'm using simulink and fixed point advisor in simulink to design this filter.... Can anyone please help..? not sure if there is another way to test the filter with a more dynamic signal. or if anyone is familiar with simulink how i can optimize my design.

A short cut is to set NCO to 10 bits then sign extend its output to16 bits

If you are working on schematics then just connect MSB of NCO to all remaing MSBs of filter input. if you want VHDL then: sine16 = std_logic_vector(resize(signed(sine11),16)); You can also keep your NCO on 16 bits then select its 11 MSBs instead of setting it to 11 bits., your choice ...

And the other option is to rescale your coeffs so that you get unity gain, set their sum to 2^15 ( or 1.0 normalised)

--- Quote Start --- If you are working on schematics then just connect MSB of NCO to all remaing MSBs of filter input. if you want VHDL then: sine16 = std_logic_vector(resize(signed(sine11),16)); You can also keep your NCO on 16 bits then select its 11 MSBs instead of setting it to 11 bits., your choice ... --- Quote End --- Wouldnt this give me a width mismatch? because i'm not sure exactly how i would do this can i get an example...i'm talking about schematic way.

NCO help... | Altera Community

36 Replies

Altera_Forum
Honored Contributor
14 years ago
I am not sure about simulink generated code. I use DSPBuilder which is based on simulink blocks but specific blocks for target devices (altera or xilinx). DSPBuilder works but simulink is not used in the industry to generate code since there is DSPBuilder ...etc.

Now the question is why the order of blocks is not right. The second issue is that of NCO which was first title posted If you suspect NCO then you can rule that out by either rescaling your FIR coeffs or you can use random data or even just one impulse (1,0,0,0..etc) at required level, pass it through model then through hardware and see the difference. At the moment you will be checking model Versus hardware so if the model is wrong functionally it will not be relevant, you only want to check model against implementation. Once done then you start to question if model is correct. You are saying that simulation works ?? how could it be if the blocks are in the wrong order... I think you need to explain your setup and results further.
Altera_Forum
Honored Contributor
14 years ago
No the blocks are in the right order, if you look at the link you see they are the same as the simulink model i posted. at this point i'm looking to do whatever it takes to make this work. i didn't know DSPbuilder was the industry standard. maybe i'll have better luck with that. how would i get this code into DSPbuilder, maybe then we'll be easier for us to be on the same page.

N = 99; [H0,H1,G0,G1] = firpr2chfb(N,.45);
% Analysis filters (decimators). Hlp = mfilt.firdecim(2,H0); Hhp = mfilt.firdecim(2,H1); % Synthesis filters (interpolators). Glp = mfilt.firinterp(2,G0); Ghp = mfilt.firinterp(2,G1);
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
No the blocks are in the right order, if you look at the link you see they are the same as the simulink model i posted.
--- Quote End ---

No that is not right. The link diagran puts H0 filter followed by down 2,
your model puts rate transition then LOwPassFilter.

Am I looking at the wrong link. Moreover it defies theory to put rate transition before decimating filter.

For DSPBuilder you will choose blocks of decimator/interpolator and connect them. You choose your coeffs as well which might well be same as your or scaled for unity gain. The rate conversion is implied in the filter itself. Once done then you run DSPBuilder to generate code and testbench.
Altera_Forum
Honored Contributor
14 years ago
My apologies, the matlab function mfilt.firdecim and mfilt.firinterp already down sample and up sample. I put the transition blocks there because I want sure if it was necessary.
Altera_Forum
Honored Contributor
14 years ago
Fair enough. But do you use the functions to generate the code or the simulink blocks. Put in other words, Does the blocks named LOwPassFilter ...etc do the rate transitions. In that case you don't need these transitions duplicated. It is a habit of diagrams makers to mislead when describing functionality !
Altera_Forum
Honored Contributor
14 years ago
Yeah there is a realizemdl function that generates them into simulink blocks, then from simulink i use the fixed point advisor tool to convert from floating point to fixed point, and then i use the HDL coder to generate HDL code. yes i do agree thats y ive been so lost i feel like ive been mislead and wasted a lot of time.

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