MooQZ
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New ContributorMy verilog code work in stimulation but not working in hardware
This is my assignment that required to design a traffic light with delays, display countdown with 7 segment display. My verilog code is working in stimulus using Modelsim but not working in Hardware(...
Hi,
project source files are incomplete, e.g. many missing modules, e.g. max21_param, counter, comparator_equal, buffer, thus can't check the design.
Notice that you don't have a testbench for top level design, without simulating the full design succesfully you can't claim that it simulates o.k.
A possible source of hardware-to-simulation mismatch is the use of ripple clocks clk_0_5s and clk 1s that may cause timing failure. Better use one system clock (50 MHz clock) together with low frequency clock enable pulses.
