My code doesnt complete synthesis

Hello i am trying to implement this code in a cyclone IV. I can't understand why it never finishes the synthesis process, i do understand that it's a lot of routing to be done but it can't even finish SYNTHESIS. And this code does work at the MODELSIM, it does exactly what i expect it to do.

The processing element which i am instantiating is an 8 bits XOR.

entity dicionario is

Port ( sys_clk : in STD_LOGIC;

sys_rst : in STD_LOGIC;

word : in STD_LOGIC_VECTOR(7 downto 0);

valid_word : in STD_LOGIC;

symbol_out : out std_logic_vector(23 downto 0)

);

end dicionario;

architecture Behavioral of dicionario is

type arr is array(0 to 2047) of std_logic_vector(7 downto 0);

type symbol_arr is array(0 to 255) of std_logic_vector(7 downto 0);

type sm_t is (WAIT_START, COUNT_WORDS, PRIORITY_ENCODER);

-- sinais do dicionario

signal match : std_logic_vector(2047 downto 0);

signal old_match : std_logic_vector(2047 downto 0);

signal search_buff : std_logic_vector(2047 downto 0);

signal lookahead_buff : std_logic_vector(63 downto 0);

signal past_words : std_logic_vector(2047 downto 0);

signal symbol : std_logic_vector(23 downto 0);

signal word_counter : natural range 0 to 2048;

signal done_reg : std_logic;

signal word_reg : std_logic_vector(7 downto 0);

signal symbol_vector : symbol_arr;

signal word_vector : arr;

signal state : sm_t;

signal set_reg : std_logic;

signal info_pack : std_logic_vector ( 31 downto 0);

constant zeroes : std_logic_vector(2047 downto 0) := (others => '0');

constant ones : std_logic_vector(2047 downto 0) := (others => '1');

COMPONENT processing_element

PORT(

sys_clk : IN std_logic;

sys_rst : IN std_logic;

set : IN std_logic;

x : IN std_logic_vector(7 downto 0);

y : IN std_logic_vector(7 downto 0);

match : OUT std_logic

);

END COMPONENT;

begin

symbol_out <= symbol;

processing_element_for:

for I in 0 to 2047 generate

Inst_processing_element : processing_element PORT MAP(

sys_clk => sys_clk,

sys_rst => sys_rst,

set => set_reg,

x => word,

y => word_vector(2047-i),

match => match(2047-i)

);

end generate processing_element_for;

process(sys_clk)

begin

if rising_edge(sys_clk) then

if sys_rst = '1' then

set_reg <= '1';

done_reg <= '0';

symbol <= (others => '0');

state <= WAIT_START;

old_match <= ( others => '0');

else

case state is

when WAIT_START =>

if valid_word = '1' then

set_reg <= '0';

if ((match /= zeroes) and (match /= ones)) then

word_counter <= word_counter + 1;

state <= COUNT_WORDS;

end if;

end if;

when COUNT_WORDS =>

if valid_word = '1' then

word_counter <= word_counter + 1;

end if;

if match = zeroes then

set_reg <= '1';

symbol <= x"00" & std_logic_vector(to_unsigned(word_counter,16));

word_counter <= 0;

state <= WAIT_START;

else

old_match <= match;

end if;

end case;

end if;

end if;

end process;

-- SHIFT REGISTER

process(sys_clk)

begin

if rising_edge(sys_clk) then

if sys_rst = '1' then

word_reg <= (others => '0');

for i in 0 to 2047 loop

word_vector(i) <= (others => '0');

end loop;

else

if valid_word = '1' then

word_reg <= word;

word_vector(2047) <= word_reg ;

for i in 0 to 2046 loop

word_vector(2047-i-1) <= word_vector(2047-i);

end loop;

end if;

end if;

end if;

end process;

end Behavioral;