Forum Discussion
Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- 1 hour - come back when it hasnt finished for 1 day. --- Quote End --- hehe i have had designs that took 2 days to compile but this seems so simple... i thought i was doing something very wrong in the RTL design but the simulation works fine and it seems to be correct (it's a Lempel–Ziv Compression algorithm for VLSI based on an article) i will try to let it compiling for a while then, tyvm