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Altera_Forum's avatar
Altera_Forum
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15 years ago

Multiplication by 0,6

Hi i have an input of 8 bits and i need to make a

multiplication by 0,6. I doesn't has to be precise so

i thaught to do :

INPUT * 19 /32

This is not a working code but is displays what i wanna do:

array_amp_to_find(column_counter) <= std_logic_vector (to_unsigned ((to_integer(CAM_DATA)*19/32), 8));

Both input (CAM_DATA) and output (array_amp_to_find) are

std_logic_vectors (7 downto 0).

Q: How to make it work in one cycle? Or first the calculation then take the 8 LSB's?

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Yea thaught so. I would be nicer to write a code in one line.

    Thx anyway!

    --- Quote End --- 

    
Library IEEE;
	use IEEE.Std_Logic_1164.all;
	use IEEE.numeric_std.all;
  . . .
dn <=  to_integer( unsigned( CAM_DATA )) ;
Q <=  std_logic_vector( to_unsigned( dn * 16 + dn * 2 +dn  , 13))(12 downto 5) ;
-- or in 1 line
Q <=  std_logic_vector( to_unsigned(  to_integer( unsigned(  CAM_DATA )) * 16 +  to_integer( unsigned(  CAM_DATA )) * 2 +  to_integer( unsigned(  CAM_DATA ))  , 13))(12 downto 5) ;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Yea thaught so. I would be nicer to write a code in one line.

    Thx anyway!
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I believe the calculation takes one clk cycle even if you use the temporary variable result,

    since the last one is a continuous assignment, not clock sensitive.

    The actual VHDL code could be:

    multiply_0_6 : process (clk, CAM_DATA)

    begin

    if (clk'event and clk='1') then

    result <= ("0" & CAM_DATA & "0000") + ("0000" & CAM_DATA & "0") + ("00000" & CAM_DATA)

    end if;

    array_amp_to_find(column_counter) <= result(12 downto 5);

    end process;

    (disclaimer: I'm not a VHDL expert, so I don't know if this is the correct syntax and if my code is actually working as supposed)
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thx,

    Does someone has an ID how to take the (12 downto 5) in the sametime

    with the calculation ?

    <= (12 dwonto 5) (("0" & CAM_DATA & "0000") + ("0000" & CAM_DATA & "0") + ("00000" & CAM_DATA));

    is not working :)
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Please note that there's no need to perform the actual /32 division. You can simply multiply 19 and discard the 5 LSB.

    Moreover multiplication *19 can be reduced to a three terms addition:

    CAM_DATA*16 + CAM_DATA*2 + CAM_DATA*1

    which is equivalent to:

    result <= ("0" & CAM_DATA & "0000") + ("0000" & CAM_DATA & "0") + ("00000" & CAM_DATA)

    where result is std_logic_vector(12 downto 0).

    Then:

    array_amp_to_find(column_counter) <= result(12 downto 5);

    So, neither an actual multiplier is required.

    I think this can be easily synthesized to work in a single cycle.

    (I'm not sure about this VHDL syntax, please check; I'm used with Verilog)

    Regards