Multiplication by 0,6

I believe the calculation takes one clk cycle even if you use the temporary variable result,

since the last one is a continuous assignment, not clock sensitive.

The actual VHDL code could be:

multiply_0_6 : process (clk, CAM_DATA)

begin

if (clk'event and clk='1') then

result <= ("0" & CAM_DATA & "0000") + ("0000" & CAM_DATA & "0") + ("00000" & CAM_DATA)

end if;

array_amp_to_find(column_counter) <= result(12 downto 5);

end process;

(disclaimer: I'm not a VHDL expert, so I don't know if this is the correct syntax and if my code is actually working as supposed)